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Static and dynamic task mapping onto network on chip multiprocessors

Bolaños-Martínez, Freddy and Aedo, Jose Edison and Rivera-Vélez, Fredy (2014) Static and dynamic task mapping onto network on chip multiprocessors. Dyna; Vol. 81, núm. 185 (2014); 28-35 DYNA; Vol. 81, núm. 185 (2014); 28-35 2346-2183 0012-7353 .

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URL oficial: http://revistas.unal.edu.co/index.php/dyna/article...

Resumen

Due to its scalability and flexibility, Network-on-Chip (NoC) is a growing and promising communication paradigm for Multiprocessor System-on-Chip (MPSoC) design. As the manufacturing process scales down to the deep submicron domain and the complexity of the system increases, fault-tolerant design strategies are gaining increased relevance. This paper exhibits the use of a Population-Based Incremental Learning (PBIL) algorithm aimed at finding the best mapping solutions at design time, as well as to finding the optimal remapping solution, in presence of single-node failures on the NoC. The optimization objectives in both cases are the application completion time and the network's peak bandwidth. A deterministic XY routing algorithm was used in order to simulate the traffic conditions in the network which has a 2D mesh topology. Obtained results are promising. The proposed algorithm exhibits a better performance, when compared with other reported approaches, as the problem size increases.

Tipo de documento:Artículo - Article
Información adicional:Derechos de autor reservados
Palabras clave:Task mapping, Multiprocessor System-on-Chip (MPSoC), Networks on Chip (NoC), Population-based Incremental Learning (PBIL).
Unidad administrativa:Revistas electrónicas UN > Dyna
Código ID:34669
Enviado por : Dirección Nacional de Bibliotecas STECNICO
Enviado el día :01 Julio 2014 16:09
Ultima modificación:18 Agosto 2014 20:47
Ultima modificación:18 Agosto 2014 20:47
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